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User's Guide
NHD-0220GZ-FL-GBW
LCM
(Liquid Crystal Display Module)
RoHS Compliant
NHD0220GZFLGBWNewhaven Display 2 Lines x 20 Characters Version Line Transflective Yellow/Green LED B/L STN-Gray 6:00 View Wide Temperature (-20 ~ +70c)
For product support, contact
Newhaven Display International, LLC 2511 Technology Drive, #101 Elgin, IL 60124
Tel: (847) 844-8795 Fax: (847) 844-8796
October 10, 2007
DOCUMENT REVISION HISTORY
Version 00 DATE Apr-06-2006 DESCRIPTION
First issue
CHANGED BY
CONTENTS Item
Functions & Features Mechanical specifications Dimensional Outline Absolute maximum ratings Block diagram Pin description Contrast adjust Optical characteristics Electrical characteristics Timing Characteristics Instruction description Display character address code: character pattern Quality Specifications
Page
3 3 4 5 5 5 6 6 6 7-8 9-12 12 13 14--21
2
NHD-0220GZ-FL-GBW
3.Outline dimension
1.0 First issue PIN ASSIGNMENT
DOTS DETAIL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GND VDD V0 RS RW E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 A K
SCALE=5:1
NHD-0220GZ-FL-GBW
Newhaven Display International, LLC
4.Absolute maximum ratings
Item P owe r volta ge I nput volta ge Operating temperature range Storage temperature range Symbol V DD -V SS V IN VOP VST 0 VS S -20 -30 Standard 7.0 V DD +70 +80 Unit V
5.Block diagram
6.Interface pin description
Pin no.
1 2 3 4 5 6 7~10 11~14 15 16
Symbol V SS V DD V0
External connection
Power supply MPU MPU MPU MPU MPU Power supply
Function
Signal ground for LCM (GND) Power supply for logic (+5V) for LCM Contrast adjust Register select signal Read/write select signal Operation (data read/write) enable signal Four low order bi-directional three-state data bus lines. Used for data transfer between the MPU and the LCM. These four are not used during 4-bit operation. Four high order bi-directional three-state data bus lines. Used for data transfer between the MPU P owe r s upply for L E D ba c k light (+5.0 V ) Power supply for LED backlight(0V)
RS R/W E
DB0~DB3 DB4~DB7 L E D+ LED-
7.Contrast adjust
VDD~V0: LCD Driving voltage VR: 10k~20k
8.Optical characteristics
TN type display module (Ta=25k, VDD=5.0V) Item Symbol Condition Viewing angle (c) Cr4 Contrast ratio Cr Response time (rise) Tr Response time (fall) Tr STN type display module (Ta=25k, VDD=5.0V) Item Symbol Condition Viewing angle (c) Cr2 Contrast ratio Cr Response time (rise) Tr Response time (fall) Tr Min. -25 -30 Min. -60
-40
Typ. 2 120 120 Typ. 6 150 150
Max. 30 150 150 Max. 35 40 250 250
Unit deg ms Unit deg ms
-
9.Electrical characteristics
DC characteristics Parameter
Supply voltage for LCD Input voltage Supply current Input leakage current "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Backlight supply voltage Backlight supply current
Symbol VDD-V0 VDD IDD ILKG VIH VIL VOH VOL VF IF
Conditions
Ta =25k Ta=25k, VDD=5.0V
Min.
4.7 2.2 0 2.4 -
Typ.
4.6 5.0 2 4.2 120
Max.
5.5 3.0 1.0 VDD 0.6 0.4 -
Unit
V mA uA
Twice initial value or less LOH=-0.25mA LOH=1.6mA
V
VF= 4.2V
mA
6
10.Timing Characteristics
Write cycle (Ta=25k, VDD=5.0V) Parameter Symbol Enable cycle time tc Enable pulse width tw Enable rise/fall time tr, tf RS; R/W setup time tsu1
RS; R/W address hold time Read data output delay Read data hold time
Test pin
E RS; R/W RS; R/W DB0~DB7
Min.
500 300 100 10 60 10
Typ.
-
Max.
25 -
Unit
ns
th1 tsu2 th2
Write mode timing diagram
VIH1 VIL1
tsu1
th1
VIL1
VIL1
tw
VIH1 VIL1 VIH1
th1 tf
VIL1 VIL1
tr
VIH1 VIL1
tsu2
VALID DATA
th2
VIH1 VIL1
tc
7
Read cycle (Ta=25k, VDD=5.0V) Parameter Symbol Enable cycle time tc Enable pulse width tw Enable rise/fall time tr, tf RS; R/W setup time tsu
RS; R/W address hold time Read data output delay Read data hold time Read mode timing diagram
VIH1 VIL1
Test pin
E RS; R/W RS; R/W DB0~DB7
Min.
500 300 100 10 60 20
Typ.
-
Max.
25 90 -
Unit
ns
th td tdh
tsu
th
VIL1
VIL1
tw
VIH1 VIL1
th tf
VIH1 VIL1
tr td
VIH1 VIL1 VALID DATA
VIL1
tdh
VIH1 VIL1
tc
8
11.Instruction description
11.1Outline To overcome the speed difference between the internal clock of KS0066U and the MPU clock, KS0066U performs internal operations by storing control in formations to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus (Refer to Table7). Instructions can be divided largely into four groups: 1) KS0066U function set instructions (set display methods, set data length, etc.) 2) Address set instructions to internal RAM 3) Data transfer instructions with internal RAM 4) Others The address of the internal RAM is automatically increased or decreased by 1. Note: during internal operation, busy flag (DB7) is read "High". Busy flag check must be preceded by the next instruction. 11.2 Instruction Table Instruction code Instruction Clear Display Return Home Entry mode Set Display ON/ OFF control Cursor or Display shift Function set Set CGRAM Address Set DDRAM Address Read busy Flag and Address Write data to Address Read data From RAM
RS DB R/W DB7 DB6 5 DB DB4 DB3 DB2 1 DB0
Description
Write "20H" to DDRA and set DDRAM address to "00H" from AC Set DDRAM address to "00H" From AC and return cursor to Its original position if shifted. The contents of DDRAM are not changed. Assign cursor moving direction And blinking of entire display
Execution time (fosc= 270 KHZ
1.53ms
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
-
1.53ms
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 D
I/D C
SH B
39us
0
0
0
0
0
0
0
0
0
0
0
1
Set display (D), cursor (C), and Blinking of cursor (B) on/off Control bit. Set cursor moving and display Shift control bit, and the 0 1 S/C R/L Direction, without changing of DDRAM data. Set interface data length (DL: 8Bit/4-bit), numbers of display 1 DL N F Line (N: =2-line/1-line) and, Display font type (F: 5x11/5x8) Set CGRAM address in AC5 AC4 AC3 AC2 AC1 AC0 address Counter. Set DDRAM address in
39us
39us
39us
0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0 address
Counter.
39us
0
1
BF
1 1
0 1
D7 D7
Whether during internal Operation or not can be known AC6 AC5 AC4 AC3 AC2 AC1 AC0 By reading BF. The contents of Address counter can also be read. Write data into internal RAM D6 D5 D4 D3 D2 D1 D0 (DDRAM/CGRAM).
0us
43us 43us
D6
D5
D4
D3
D2
D1
D0
Read data from internal RAM (DDRAM/CGRAM).
NOTE: When an MPU program with checking the busy flag (DB7) is made, it must be necessary 1/2fosc is necessary for executing the next instruction by the falling edge of the "E" signal after the busy flag (DB7) goes to "Low".
9
11.3Contents 1) Clear display RS R/W 0 0
DB7 0
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 0
DB0 1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on the fist line of the display. Make the entry mode increment (I/D="High"). 2) Return home RS R/W DB7 DB6 DB5 DB4 DB3 DB2 0 0 0 0 0 0 0 0 Return home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. Entry mode set RS R/W 0 0
DB1 1
DB0 -
3)
DB7 0
DB6 0
DB5 0
DB4 0
DB3 0
DB2 1
DB1 I/D
DB0 SH
Set the moving direction of cursor and display. I/D: increment / decrement of DDRAM address (cursor or blink) When I/D="high", cursor/blink moves to right and DDRAM address is increased by 1. When I/D="Low", cursor/blink moves to left and DDRAM address is increased by 1. *CGRAM operates the same way as DDRAM, when reading from or writing to CGRAM. SH: shift of entire display When DDRAM read (CGRAM read/write) operation or SH="Low", shifting of entire display is not performed. If SH ="High" and DDRAM write operation, shift of entire display is performed according to I/D value. (I/D="high". shift left, I/D="Low". Shift right). Display ON/OFF control RS R/W DB7 DB6 DB5 0 0 0 0 0 Control display/cursor/blink ON/OFF 1 bit register. 4)
DB4 0
DB3 1
DB2 D
DB1 C
DB0 B
D: Display ON/OFF control bit When D="High", entire display is turned on. When D="Low", display is turned off, but display data remains in DDRAM. C: cursor ON/OFF control bit When D="High", cursor is turned on. When D="Low", cursor is disappeared in current display, but I/D register preserves its data. B: Cursor blink ON/OFF control bit When B="High", cursor blink is on, which performs alternately between all the "High" data and display characters at the cursor position. When B="Low", blink is off. Cursor or display shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 0 0 0 0 0 1 S/C R/L Shifting of right/left cursor position or display without writing or reading of display data. This instruction is used to correct or search display data. During 2-line mode display, cursor moves to the 2nd line after the 40th digit of the 1st line. Note that display shift is performed simultaneously in all the lines.
10
5)
DB0 -
When display data is shifted repeatedly, each line is shifted individually. When display shift is performed, the contents of the address counter are not changed. Shift patterns according to S/C and R/L bits S/C 0 0 1 1 6) R/L 0 1 0 1 Operation Shift cursor to the left, AC is decreased by 1 Shift cursor to the right, AC is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
Function set RS R/W 0 0
DB7 0
DB6 0
DB5 1
DB4 DL
DB3 N
DB2 F
DB1 -
DB0 -
DL: Interface data length control bit When DL="High", it means 8-bit bus mode with MPU. When DL="Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. When 4-but bus mode, it needs to transfer 4-bit data twice. N: Display line number control bit When N="Low", 1-line display mode is set. When N="High", 2-line display mode is set. F: Display line number control bit When F="Low", 5x8 dots format display mode is set. When F="High", 5x11 dots format display mode. 7) Set CGRAM address RS R/W DB7 0 0 0
DB6 1
DB5 AC5
DB4 AC4
DB3 AC3
DB2 AC2
DB1 AC1
DB0 AC0
Set CGRAM address to AC. The instruction makes CGRAM data available from MPU. 8) Set DDRAM address RS R/W DB7 0 0 1
DB6 AC6
DB5 AC5
DB4 AC4
DB3 AC3
DB2 AC2
DB1 AC1
DB0 AC0
Set DDRAM address to AC. This instruction makes DDRAM data available form MPU. When 1-line display mode (N=LOW), DDRAM address is form "00H" to "4FH".In 2-line display mode (N=High), DDRAM address in the 1st line form "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". 9) Read busy flag & address RS R/W DB7 0 1 BF
DB6 AC6
DB5 AC5
DB4 AC4
DB3 AC3
DB2 AC2
DB1 AC1
DB0 AC0
This instruction shows whether KS0066U is in internal operation or not. If the resultant BF is "High", internal operation is in progress and should wait BF is to be LOW, which by then the nest instruction can be performed. In this instruction you can also read the value of the address counter. 10) Write data to RAM RS R/W DB7 1 0 D7
DB6 D6
DB5 D5
DB4 D4
DB3 D3
DB2 D2
DB1 D1
DB0 D0
Write binary 8-bit data to DDRAM/CGRAM.
11
The selection of RAM from DDRAM, and CGRAM, is set by the previous address set instruction (DDRAM address set, CGRAM address set). RAM set instruction can also determine the AC direction to RAM. After write operation. The address is automatically increased/decreased by 1, according to the entry mode. 11) Read data from RAM RS R/W DB7 1 1 D7
DB6 D6
DB5 D5
DB4 D4
DB3 D3
DB2 D2
DB1 D1
DB0 D0
Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not performed before this instruction, the data that has been read first is invalid, as the direction of AC is not yet determined. If RAM data is read several times without RAM address instructions set before, read operation, the correct RAM data can be obtained from the second. But the first data would be incorrect, as there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction, it also transfers RAM data to output data register. After read operation, address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. NOTE: In case of RAM write operation, AC is increased/decreased by 1 as in read operation. At this time, AC indicates next address position, but only the previous data can be read by the read instruction.
12.Display character address code:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
12
13.Standard character pattern
13
14.QUALITY SPECIFICATIONS 14.1 Standard of the product appearance test
Manner of appearance test: The inspection should be performed in using 20W x 2 fluorescent lamps. Distance between LCM and fluorescent lamps should be 100 cm or more. Distance between LCM and inspector eyes should be 30 cm or more. Viewing direction for inspection is 45 from vertical against LCM.
Fluorescent Lamps 30cm
o 45 o 45 min
100cm min
LCM
LCD
Definition of zone:
A Zone B Zone A Zone: Active display area (minimum viewing area). B Zone: Non-active display area (outside viewing area).
14
14.2 Specification of quality assurance
AQL inspection standard
Sampling method: MIL-STD-105E, Level II, single sampling Defect classification (Note: * is not including)
Classify Major Display state
Item Short or open circuit LC leakage Flickering No display Wrong viewing direction Contrast defect (dim, ghost) Back-light Non-display Flat cable or pin reverse Wrong or missing component
Note 1
AQL 0.65
2 1,8 10 11 2 3 4 5 6 7 1.0
Minor
Display state
Background color deviation Black spot and dust Line defect, Scratch Rainbow Chip Pin hole Protruded
12 3 9 10 13
Polarizer Soldering Wire TAB
Bubble and foreign material Poor connection Poor connection Position, Bonding strength
15
Note on defect classification
No. 1
Item Short or open circuit LC leakage Flickering No display Wrong viewing direction Wrong Back-light
Criterion Not allow
2
Contrast defect Background deviation color
Refer to approval sample
3
Point defect, Black spot, dust (including Polarizer)
Y X
Point Size <0.10 0.10<0.20 0.20<0.25 0.25<0.30 >0.30
Acceptable Qty.
Disregard 3 2 1 0 Unit mm
= (X+Y)/2
4
Line defect, Scratch
L
W
Line L W --0.015W 3.0L 0.03W 2.0L 0.05W 1.0L 0.1 W
--0.05Acceptable Qty.
Disregard 2 1
Applied as point defect
Unit: mm 5 Rainbow Not more than two color changes across the viewing area.
16
No 6 Chip
Item
Criterion
X
Remark: X: Length direction Y: Short direction Z: Thickness direction t: Glass thickness W: Terminal Width
Y
Z
t
Acceptable criterion X Y 0.5mm 2
Z 9/2
X
Y
Acceptable criterion X Y 0.5mm 2
Z 9
Z
Acceptable criterion X Y 3 2 Y X
shall not reach to ITO
Z 9
W
Y
Z X
Acceptable criterion X Y Disregard 0.2
Z 9
Y
Acceptable criterion X Y
Z t/3
X
Z
17
No. 7
Item Segment pattern W = Segment width = (X+Y)/2 (1) Pin hole
Criterion
< 0.10mm is acceptable. X
X
Point Size W
Y
Acceptable Qty Disregard 1 0 Unit: mm
Y W< W W W 8 Back-light
(1) The color of specification.
backlight
should
correspond
its
(2) Not allow flickering 9 Soldering (1) Not allow heavy dirty and solder ball on PCB. (The size of dirty refer to point and dust defect) (2) Over 50% of lead should be solderedon Land.
Lead Land 50% lead
10
Wire
(1) Copper wire should not be rusted (2) Not allow crack on copper wire connection. (3) Not allow reversing the position of the flat cable. (4) Not allow exposed copper wire inside the flat cable.
11*
PCB
(1) Not allow screw rust or damage. (2) Not allow missing or wrong putting of component.
18
No 12
Item Protruded W: Terminal Width
Criterion
W
Acceptable criteria:
Y
Y 0.4
X 13 TAB 1. Position W H H1 2 TAB bonding strength test F TAB W1 ITO W11/3W H11/3H
TAB
P (=F/TAB bonding width) 650gf/cm ,(speed rate: 1mm/min) 5pcs per SOA (shipment)
14
Total no. of acceptable Defect
A. Zone Maximum 2 minor non-conformities per one unit. Defect distance: each point to be separated over 10mm B. Zone It is acceptable when it is no trouble for quality and assembly in customer's end product.
19

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